*Neuromorphic CPU (Generations) After the RISC-V CPU for open source programming for Intelligent CPUs

  1. 1st Generation CPU No Ram

  2. 2nd Generation CPU + GPU No Ram

  3. 3rd Generation CPU + GPU No Ram with Sampling

  4. 4th Generation CPU + GPU No Ram with Sampling + Memory Address linked to 3D Database of I/O NVME SSD

  5. 5th Generation CPU + GPU No Ram with Sampling + Memory Address linked to 3D Database of I/O NVME SSD + Multiple Clusters

  6. 6th Generation 7nm CPU + GPU(Data Frame, 16 pipes) No Ram with Sampling + Memory Address linked to 3D Database of I/O NVME SSD + Multiple Clusters (80 CPUs)(Linked Instruction sets + Kernel – Stacking)

  7. 7th Generation 5nm CPU (Eitching process)+ GPU(Data Frame, 16 pipes) No Ram with Sampling + Memory Address linked to 3D Database of I/O NVME SSD + Multiple Clusters (80 CPUs)(Linked Instruction sets + Kernel – Stacking)

  8. 8th Generation 5nm CPU (Eitching process)+ GPU(Data Frame, 64 pipes) No Ram with Sampling + Memory Address linked to 3D Database of I/O NVME SSD + Multiple Clusters (80 CPUs)(Linked Instruction sets + Kernel – Stacking)

  9. 9th Generation 5nm CPU (Eitching process)+ GPU(Data Frame, 64 pipes) No Ram with Sampling + Memory Address linked to 3D Database of I/O NVME SSD + Multiple Clusters (80 CPUs)(Linked Instruction sets + Kernel – Stacking)(Control Stack intergrated + App stack for 3D Search Engine + Virtualization) Testing on Mining Rigs on Bitcoin without Blockchain 3.0

  10. 10th Generation 5nm CPU (Eitching process)+ GPU(Data Frame, 64 pipes) No Ram with Sampling + Memory Address linked to 3D Database of I/O NVME SSD + Multiple Clusters (160 CPUs)(Linked Instruction sets + Kernel – Stacking)(Control Stack intergrated + App stack for 3D Search Engine + Virtualization) + Oscillascope for Consistent Hashing prior to Blockchain 3.0

  11. After 2023. Neuromorphic 5nm CPU (Node) – The entire System in a Chip. CPU + GPU/Display + Sound + Network + WiFi

  12. After 2023. Neuromorphic 5nm CPU (80 Cluster – DataCentre) – The  Multiple Cluster CPU. Chipset. GPU/Display + Sound + Network + WiFi

  13. After 2023. Neuromorphic 5nm CPU (Cluster – The Edge – iOT) – The  Edge Cluster 8/16/24/36 CPU. Chipset. GPU/Display + Sound + Network + WiFi

Testing Maya Software 16K Highest resolution output possible. It is beyond SGI, beyond any supercomputer found in Watt Disney Studios. I ain’t finnished yet. My goal is 100x faster than a supercomputer.

Respective owners of copyright :

@ARM and AMD for efficient low power technology for multiple cores CPU.

@Nvidia for GPU dataframes and pipes

@UN China. Sampling for Neuromorphic

@UN China. Memory addressing linked to I/O for NVME SSD

@ UN China. Linked Instruction sets and Kernel for Clustering and Multi-threadng using stacking (Beyond AMD Threadripper can do)

*Pushing the limits to beyond 100X of a Supercomputer

*Copyright due to United Nations China

Prior to launching my Neuromorphic platform on Intelligent OS, RISC- V will be platform I will customised for both hardware/software to optimsed everything to reach 100x the fastest supercomputer today. Contributed by Oogle.

Hello RISC-V Community!
We’ve made tremendous progress in RISC-V across the first months of 2020 and I am grateful to this community for coming together, making bold strides forward, and engaging deeply in RISC-V. I hope this message finds you healthy in an unprecedented time of global concern.

In the March we initiated our member transition to our new legal entity, RISC-V International and we’ve already seen more than a third of our organization members sign on. The value we bring as RISC-V to engagement and strategic importance continues to grow and our programs to support all stakeholders are in motion. Today we’re pleased to launch the Community individual option for sign-up of individuals in our RISC-V community that are not part of a legal entity. To learn about membership value and sign up for any membership level, please visit the RISC-V Membership page.

As we continue the transition, we’ve already welcomed new premier members and their respective Board directors, highlighted on our Leadership page. We’ve also launched our Technical Steering Committee to govern our technical committees and work groups, with new work groups coming online, streamlining the development process, and ensuring a clear path for the many technical deliverables across our RISC-V community.

On visibility, we’ve engaged in many press and analyst opportunities as well as events, both in-person and growing online events. We’ve launched the call for speakers for our 2020 RISC-V Summit, with more detail for speakers and sponsors available online. We’re also planning for an online Global RISC-V Forum in September, stay tuned for details on date, call for speakers, and sponsorship opportunities. Please continue to follow us on our website, Twitter, and LinkedIn.

Call to Action!
We are now calling for nominations to represent the RISC-V International Strategic and Premier TSC members as well as Community members on the RISC-V Board of Directors!

RISC-V International welcomes and thanks all members who have made the transition to the new organization. We want to encourage members to participate in RISC-V governance, as outlined in the new member benefits. Going forward, all RISC-V International members will have a voice on the Board of Directors through representation by elected members for each membership level. If you have not yet signed up for the new membership, please take a minute to do so and let us know if you encounter any challenge.

Nominations are welcome now through June 30. Voting will take place July 1 – July 31, with new representatives installed at the board meeting on August 20. You can nominate yourself or another member using the form online and candidates will be featured on our website. The following seats will be elected:

– 3 Director representatives for Strategic & Premier TSC members
– 1 Director representative for Community Organization members
– 1 Director representative for Community Individual members

Board membership is an important responsibility. Elected Directors must attend all board meetings, which are currently held at 5pm Pacific time on the third Thursday of each month. At these meetings, they will represent the other RISC-V members at their level in discussions as well as votes, and to make themselves available for regular communication with the other members at their level. Representatives will vote on behalf of their membership tier, not for their specific companies. For more guidance on board member expectations and requirements, see Article 1 of the Internal Regulations.

Each board seat lasts for one year, provided that the Director’s organization remains a member in good standing during that time. All members of RISC-V International in good standing may nominate representatives between now and June 30. All members of RISC-V International in good standing between July 1 – 31 may vote on the nominations. Ballot links will be sent to the voting member of record on July 1. Each member may vote only once. For those members unable to vote using this method, we can accommodate votes by email. Please note that nominations and votes can only be recorded by members of RISC-V International.

These are the important dates for this election:
– Now through June 30: nominations accepted
– June 30: last day for nominations
– July 1: first day of voting
– July 31: final day of voting
– August 20: first board meeting to include new representative Directors

I’m incredibly proud to lead RISC-V International as we usher in the next era of computing together with stakeholders around the world. I look forward to continuing our progress and invite you to follow me on social media and reach out directly at any time.

Best
Calista


Calista Redmond
CEO RISC-V International

+1-202-489-5878
calista@riscv.org
calista@linuxfoundation.org
twitter @calista_redmond